Pprocessing of polycrystalline diamond wafers through removing growth stress
May31, 2025
Processing of polycrystalline diamond wafers through removing growth stress
Polycrystalline diamond wafers exhibit considerable application potential in heat dissipation components and high-power electronic devices due to their exceptional physical properties. However, stress accumulation during wafer growth and the complexity of surface grain boundaries—such as impurity segregation and large grain formation—pose significant challenges for subsequent machining. This study introduces a metal oxide pretreatment method designed to inhibit anisotropic reactions and carbide formation during metal-based surface modification. Thermogravimetric analysis of NiO, FeO, and CuO was conducted to determine optimal reaction conditions. Among these, CuO pretreatment at 550 °C effectively facilitated the release of growth-induced stress in the wafer's surface layer, resulting in the removal of a 5.875 μm reaction layer. Post-treatment, wafers processed via self-rotating grinding exhibited significantly enhanced surface quality and a twofold increase in material removal rate, offering a promising strategy for the efficient machining of polycrystalline diamond wafers.
Introduction
Diamond wafers are emerging as promising substrates for third-generation semiconductor materials , owing to their low dielectric constant , superior optical transparency , exceptional thermal conductivity , and wide bandgap . Despite complexities in growth mechanisms, both single-crystal and polycrystalline diamond wafers have attracted significant industrial interest. Polycrystalline diamond wafers synthesized through advanced techniques such as hot filament chemical vapor deposition (HF-CVD) , microwave plasma-assisted chemical vapor deposition (MPCVD) , and plasma-enhanced chemical vapor deposition (PECVD) are particularly suited for high-performance heat sinks and thermal management in high-power devices. However, growth-induced stress and complex surface grain boundary structures hinder their machinability , necessitating improved processing strategies to ensure precision and efficiency.
In single-crystal diamond wafer processing, a solid-state pretreatment technique involving thermal interaction with metals has shown promise in mitigating grinding and polishing challenges while reducing the risk of wafer fracture from internal stress. This process forms a detachable reaction layer on the wafer surface, thereby simplifying processing and adjusting the surface stress state. For instance, Norio Tokuda et al. demonstrated that thermal treatment with Ni on (100)-oriented single-crystal diamond wafers generates a graphite layer that enables ultra-smooth surfaces at the 0.62 nm level. Similarly, Cr-based treatments have been used to reduce internal stress, though they often exhibit undesirable anisotropic reactions. Graphitizing metals like Ni and Co, as well as carbide-forming elements such as Ti and Cr, are commonly applied for surface modification in diamond tool fabrication and thin-film growth . While these active metal reactions help relieve internal stress, their layer-by-layer etching approach can hinder surface planarity and overall efficiency.
To overcome these limitations, a low-damage method capable of directly removing surface grains and eliminating growth stress is critical for advancing the machining of polycrystalline diamond wafers. Rebecca et al. reported the beneficial encapsulation effects of metal oxides on diamond wafers, and Wang et al. confirmed the etching capability of metal oxides on diamond surfaces. Preliminary studies from our group demonstrated that CuO can react with single-crystal diamond surfaces to produce amorphous carbon, a finding supported by theoretical calculations under zero-Kelvin conditions Additional theoretical studies indicate that NiO, CuO, and FeO are highly reactive with diamond surfaces. Accordingly, we investigated the use of these metal oxides as pretreatment agents to modify the surface grains of polycrystalline diamond wafers.
Diamond semiconductor researching institute
Fremont, California
