Scalable Electrostatic-Trapping of Single Nanodiamonds for Quantum Device Integration

Scalable Electrostatic-Trapping of Single Nanodiamonds for Quantum Device Integration

Summary

Nanodiamonds (NDs) with nitrogen-vacancy (NV) centers are promising building blocks for quantum sensing, imaging, and communication technologies. However, precisely positioning single NDs on diverse substrates at large scale remains a major challenge due to their heterogeneous size, shape, and surface chemistry.

This work presents a simple, CMOS-compatible electrostatic-trapping method that enables rapid, reliable, and scalable patterning of single ND arrays on arbitrary substrates. Using engineered microscale hole templates with tailored electrostatic fields, negatively charged NDs are selectively trapped at the center of positively charged holes through electrostatic attraction. The process achieves 82.5% single-ND yield across an 8-inch silicon wafer within just 5 minutes, significantly outperforming existing ND placement methods.

Mechanism and Process

The method relies on creating an hourglass-shaped electrostatic potential gradient inside the template holes. The hole bottom is positively charged via amino (NH₃⁺) surface functionalization, while the sidewalls remain negatively charged. Negatively charged, -COOH-functionalized NDs migrate along the potential gradient and become stably anchored at the hole center. Both experiments and COMSOL-based Poisson–Boltzmann simulations confirm that the electrostatic potential decays from the edge to the center, defining a narrow “trapping zone” that captures a single ND. The number of trapped NDs depends mainly on hole diameter, not depth.

Results

Large-area SEM and optical imaging demonstrate uniform, contamination-free ND arrays across wafer-scale surfaces. The method shows high reproducibility (validated across multiple 25×25 ND arrays) and tunable trapping by varying hole diameter. Furthermore, Kelvin probe force microscopy verifies that trapping is driven by electrostatic absorption between positively charged hole bottoms and negatively charged NDs.

Compatibility and Impact

The electrostatic-trapping process is fully compatible with standard CMOS microfabrication and heterogeneous quantum platforms, including silicon waveguides, GaN pillars, and gold microwave antennas. The trapped NDs remain stably positioned after template removal, demonstrating robust integration.

This scalable and versatile approach bridges the gap between laboratory research and industrial-scale manufacturing of ND-based quantum devices. It provides a universal, low-cost strategy for fabricating ordered quantum emitter arrays, paving the way for mass-producible quantum sensors, photonic circuits, and communication chips.